Article : texte imprimé

A Hardware Accelerator and FPGA realization for reduced visibility graph construction using efficient bit representations

Sridharan, K., Auteur ; Priya, T.K., Auteur |

Dans IEEE transactions on industrial electronics (Vol. 54 N°3, Juin 2007)

The reduced visibility graph (RVG) is an important structure for computation of shortest paths for mobile robots. An efficient bit representation is proposed to construct segments that are part of the RVG. Based on the bit representation, a hard[...]

Plus d'information...

Ajouter un tag

En ligne

---

1 (1 - 1 / 1) Par page : 25 50 100 200