Dépouillements

Multimedia IP architecture trends in the mobile multimedia consumer device / J. Meehan in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 317–324 Titre : Multimedia IP architecture trends in the mobile multimedia consumer device Type de document : texte imprimé Auteurs : J. Meehan, Auteur ; S. Busch, Auteur ; J. Noel, Auteur Année de publication : 2012 Article en page(s) : pp. 317–324 Note générale : Electronique Langues : Anglais (eng) Mots-clés : Mobile  consumer  device  Media  processor  Architecture  Imaging  Video  Graphics  Display Résumé : A dedicated media processor is used in many mobile consumer devices to accelerate video, image, graphics, and display processing. Increased demand for higher pixel resolution, higher quality image and video processing, more graphics performance necessitates dramatically increased signal processing capabilities. To provide the increased performance at acceptable cost and power requires redesign of the traditional architecture. By wisely partitioning algorithms across programmable and fixed-function blocks, the performance goals can be met while still maintaining flexibility for new feature requirements and new standards. For a better than acceptable user experience and playback time, all IPs (display, graphics, video, and imaging) have to be optimized as an “end to end” system. In this paper, an overview of the future trends of multimedia IP processor architectures is provided that describes the implications on system architecture, power, and performance. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000433 [article] Multimedia IP architecture trends in the mobile multimedia consumer device [texte imprimé] / J. Meehan, Auteur ; S. Busch, Auteur ; J. Noel, Auteur . - 2012 . - pp. 317–324. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 317–324 Mots-clés : Mobile  consumer  device  Media  processor  Architecture  Imaging  Video  Graphics  Display Résumé : A dedicated media processor is used in many mobile consumer devices to accelerate video, image, graphics, and display processing. Increased demand for higher pixel resolution, higher quality image and video processing, more graphics performance necessitates dramatically increased signal processing capabilities. To provide the increased performance at acceptable cost and power requires redesign of the traditional architecture. By wisely partitioning algorithms across programmable and fixed-function blocks, the performance goals can be met while still maintaining flexibility for new feature requirements and new standards. For a better than acceptable user experience and playback time, all IPs (display, graphics, video, and imaging) have to be optimized as an “end to end” system. In this paper, an overview of the future trends of multimedia IP processor architectures is provided that describes the implications on system architecture, power, and performance. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000433

Architectures for multi-threaded MVC-compliant multi-view video decoding and benchmark tests / C. Goktug Gurler in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 325–334 Titre : Architectures for multi-threaded MVC-compliant multi-view video decoding and benchmark tests Type de document : texte imprimé Auteurs : C. Goktug Gurler, Auteur ; Anil Aksay, Auteur ; Gozde Bozdagi Akar, Auteur Année de publication : 2012 Article en page(s) : pp. 325–334 Note générale : Electronique Langues : Anglais (eng) Mots-clés : MVC  Decoding  Multi-threaded  Multi-core  Real-time Résumé : 3D video based on stereo/multi-view representations is becoming widely popular. Real-time encoding/decoding of such video is an important concern as the number and spatial/temporal resolution of views increase. We present a systematic method for design and optimization of multi-threaded multi-view video encoding/decoding algorithms using multi-core processors and provide benchmark results for real-time decoding. The proposed multi-core decoding architectures are compliant with the current MVC extension of H.264/AVC international standard, and enable multi-threaded processing with negligible loss of encoding efficiency and minimum processing overhead. Benchmark results show that multi-core processors and multi-threading decoding are necessary for real-time high-definition multi-view video decoding and display. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000032 [article] Architectures for multi-threaded MVC-compliant multi-view video decoding and benchmark tests [texte imprimé] / C. Goktug Gurler, Auteur ; Anil Aksay, Auteur ; Gozde Bozdagi Akar, Auteur . - 2012 . - pp. 325–334. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 325–334 Mots-clés : MVC  Decoding  Multi-threaded  Multi-core  Real-time Résumé : 3D video based on stereo/multi-view representations is becoming widely popular. Real-time encoding/decoding of such video is an important concern as the number and spatial/temporal resolution of views increase. We present a systematic method for design and optimization of multi-threaded multi-view video encoding/decoding algorithms using multi-core processors and provide benchmark results for real-time decoding. The proposed multi-core decoding architectures are compliant with the current MVC extension of H.264/AVC international standard, and enable multi-threaded processing with negligible loss of encoding efficiency and minimum processing overhead. Benchmark results show that multi-core processors and multi-threading decoding are necessary for real-time high-definition multi-view video decoding and display. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000032

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators / Yiran Li in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 335–344 Titre : Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators Type de document : texte imprimé Auteurs : Yiran Li, Auteur ; Yang Liu, Auteur ; Tong Zhang, Auteur Année de publication : 2012 Article en page(s) : pp. 335–344 Note générale : Electronique Langues : Anglais (eng) Mots-clés : Motion  estimation  (ME)  3D  memory  stacking Résumé : Enabled by the emerging three-dimensional (3D) integration technologies, 3D integrated computing platforms that stack high-density DRAM die(s) with a logic circuit die appear to be attractive for memory-hungry applications such as multimedia signal processing. This paper considers the design of motion estimation accelerator under a 3D logic-DRAM integrated heterogeneous multi-core system framework. In this work, we develop one specific DRAM organization and image frame storage strategy geared to motion estimation. This design strategy can seamlessly support various motion estimation algorithms and variable block size with high energy efficiency. With a DRAM performance modeling/estimation tool and ASIC design at 65 nm, we demonstrate the energy efficiency of such 3D integrated motion estimation accelerators with a case study on HDTV multi-frame motion estimation. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000469 [article] Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators [texte imprimé] / Yiran Li, Auteur ; Yang Liu, Auteur ; Tong Zhang, Auteur . - 2012 . - pp. 335–344. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 335–344 Mots-clés : Motion  estimation  (ME)  3D  memory  stacking Résumé : Enabled by the emerging three-dimensional (3D) integration technologies, 3D integrated computing platforms that stack high-density DRAM die(s) with a logic circuit die appear to be attractive for memory-hungry applications such as multimedia signal processing. This paper considers the design of motion estimation accelerator under a 3D logic-DRAM integrated heterogeneous multi-core system framework. In this work, we develop one specific DRAM organization and image frame storage strategy geared to motion estimation. This design strategy can seamlessly support various motion estimation algorithms and variable block size with high energy efficiency. With a DRAM performance modeling/estimation tool and ASIC design at 65 nm, we demonstrate the energy efficiency of such 3D integrated motion estimation accelerators with a case study on HDTV multi-frame motion estimation. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000469

Lossless image compression using adjustable fractional line-buffer / Salih Dikbas in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 345–351 Titre : Lossless image compression using adjustable fractional line-buffer Type de document : texte imprimé Auteurs : Salih Dikbas, Auteur ; Fan Zhai, Auteur Année de publication : 2012 Article en page(s) : pp. 345–351 Note générale : Electronique Langues : Anglais (eng) Mots-clés : Lossless  compression  Low-complexity  Embedded  systems  SoC Résumé : Video frame memory compression has gained increased popularity in video processing ICs to save external memory storage size and reduce memory access bandwidth. This technique is especially important in portable devices where efficient use of energy is critical for the deployment of video applications. In this paper, we propose a low-complexity lossless image compression method that uses only a fraction of one line-buffer. The proposed method first employs integer wavelet transform (IWT), and then low-frequency coefficients prediction of each segment based on those from the segment in the line above, and last Golomb-Rice (GR) encoding to achieve low-cost and highly efficient compression. Simulation results demonstrate that the proposed method gives a compression ratio comparable with the existing state-of-the-art low-complexity methods while significantly lowering the internal memory cost and keeping the complexity low. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000317 [article] Lossless image compression using adjustable fractional line-buffer [texte imprimé] / Salih Dikbas, Auteur ; Fan Zhai, Auteur . - 2012 . - pp. 345–351. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 345–351 Mots-clés : Lossless  compression  Low-complexity  Embedded  systems  SoC Résumé : Video frame memory compression has gained increased popularity in video processing ICs to save external memory storage size and reduce memory access bandwidth. This technique is especially important in portable devices where efficient use of energy is critical for the deployment of video applications. In this paper, we propose a low-complexity lossless image compression method that uses only a fraction of one line-buffer. The proposed method first employs integer wavelet transform (IWT), and then low-frequency coefficients prediction of each segment based on those from the segment in the line above, and last Golomb-Rice (GR) encoding to achieve low-cost and highly efficient compression. Simulation results demonstrate that the proposed method gives a compression ratio comparable with the existing state-of-the-art low-complexity methods while significantly lowering the internal memory cost and keeping the complexity low. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000317

Algorithmic and software techniques for embedded vision on programmable processors / Branislav Kisačanin in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 352–362 Titre : Algorithmic and software techniques for embedded vision on programmable processors Type de document : texte imprimé Auteurs : Branislav Kisačanin, Auteur ; Zoran Nikolić, Auteur Année de publication : 2012 Article en page(s) : pp. 352–362 Note générale : Electronique Langues : Anglais (eng) Mots-clés : Real-time  Embedded  Vision  Programmable  DSP Résumé : In the last few years, programmable architectures centered around high-end DSP processors have emerged as the platform of choice for high-volume embedded vision applications, such as automotive safety and video surveillance. Their programmability inherently addresses the problems presented by the sheer diversity of vision algorithms. This paper provides an overview of high-impact algorithmic and software techniques for embedded vision applications implemented on programmable architectures and discusses several system-level issues. We provide a general discussion and practical examples for the following categories of algorithmic techniques: fast algorithms, reduced dimensionality and mathematical shortcuts. Additionally, we discuss the importance of software techniques such as the use of fixed-point arithmetic, reduced data transfers and cache-friendly programming. In our experience, each of these techniques is a key enabler for real-time embedded vision systems. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000305 [article] Algorithmic and software techniques for embedded vision on programmable processors [texte imprimé] / Branislav Kisačanin, Auteur ; Zoran Nikolić, Auteur . - 2012 . - pp. 352–362. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 352–362 Mots-clés : Real-time  Embedded  Vision  Programmable  DSP Résumé : In the last few years, programmable architectures centered around high-end DSP processors have emerged as the platform of choice for high-volume embedded vision applications, such as automotive safety and video surveillance. Their programmability inherently addresses the problems presented by the sheer diversity of vision algorithms. This paper provides an overview of high-impact algorithmic and software techniques for embedded vision applications implemented on programmable architectures and discusses several system-level issues. We provide a general discussion and practical examples for the following categories of algorithmic techniques: fast algorithms, reduced dimensionality and mathematical shortcuts. Additionally, we discuss the importance of software techniques such as the use of fixed-point arithmetic, reduced data transfers and cache-friendly programming. In our experience, each of these techniques is a key enabler for real-time embedded vision systems. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000305

An attention controlled multi-core architecture for energy efficient object recognition / Joo-Young Kim in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 363–376 Titre : An attention controlled multi-core architecture for energy efficient object recognition Type de document : texte imprimé Auteurs : Joo-Young Kim, Auteur ; Sejong Oh, Auteur ; Seungjin Lee, Auteur Année de publication : 2012 Article en page(s) : pp. 363–376 Note générale : Electronique Langues : Anglais (eng) Mots-clés : Attention  controlled  Multi-core  architecture  Object  recognition  Visual  attention  Energy  efficient Résumé : In this paper, an attention controlled multi-core architecture is proposed for energy efficient object recognition. The proposed architecture employs two IP layers having different roles for energy efficient recognition processing: the attention/control IPs compute regions-of-interest (ROIs) of the entire image and control the multiple processing cores to perform local object recognition processing on selected area. To this end, a task manager is proposed to perform dynamic scheduling of various ROI tasks from the attention IP to multiple cores in a unit of small-sized grid-tile. Thanks to a number of grid-tile threads generated by the task manager, the utilization of the multiple cores amounts to 92% on average. As a result, the proposed architecture achieves 2.1× energy reduction in multi-core recognition system by indicating processing cores to focus on critical area of the image with a 0.87 mJ attention processing. Finally, the proposed architecture is implemented in 0.13 μm CMOS technology and the fabricated chip verifies 3.2× lower energy dissipation per frame than the state-of-the-art object recognition processor. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000342 [article] An attention controlled multi-core architecture for energy efficient object recognition [texte imprimé] / Joo-Young Kim, Auteur ; Sejong Oh, Auteur ; Seungjin Lee, Auteur . - 2012 . - pp. 363–376. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 363–376 Mots-clés : Attention  controlled  Multi-core  architecture  Object  recognition  Visual  attention  Energy  efficient Résumé : In this paper, an attention controlled multi-core architecture is proposed for energy efficient object recognition. The proposed architecture employs two IP layers having different roles for energy efficient recognition processing: the attention/control IPs compute regions-of-interest (ROIs) of the entire image and control the multiple processing cores to perform local object recognition processing on selected area. To this end, a task manager is proposed to perform dynamic scheduling of various ROI tasks from the attention IP to multiple cores in a unit of small-sized grid-tile. Thanks to a number of grid-tile threads generated by the task manager, the utilization of the multiple cores amounts to 92% on average. As a result, the proposed architecture achieves 2.1× energy reduction in multi-core recognition system by indicating processing cores to focus on critical area of the image with a 0.87 mJ attention processing. Finally, the proposed architecture is implemented in 0.13 μm CMOS technology and the fabricated chip verifies 3.2× lower energy dissipation per frame than the state-of-the-art object recognition processor. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000342

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores / B. Krill in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 377–387 Titre : An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores Type de document : texte imprimé Auteurs : B. Krill, Auteur ; A. Ahmad, Auteur ; A. Amira, Auteur Année de publication : 2012 Article en page(s) : pp. 377–387 Note générale : Electronique Langues : Anglais (eng) Mots-clés : Dynamic  partial  reconfiguration  (DPR)  Design  flow  Field  programmable  gate  array  (FPGA)  IP  cores  Image  and  signal  processing Résumé : This paper describes a dynamic partial reconfiguration (DPR) design flow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design flow, important features such as overall flexibility, application and standardised interfaces, host applications and DPR area/size placement have been taken into consideration in the proposed design flow and environment. Three intellectual property (IP) cores used in pre-processing and transform blocks of compression systems including colour space conversion (CSC), two-dimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar wavelet transform (3-D HWT) have been selected to validate the proposed DPR design flow and environment. Results obtained reveal that the proposed environment has a better solution providing: a scriptable program to establish the communication between the field programmable gate array (FPGA) with IP cores and their host application, power consumption estimation for partial reconfiguration area and automatic generation of the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of efficient IP cores with optimised area/speed ratios. Analysis of the bitstream size and dynamic power consumption for both static and reconfigurable areas is also presented in this paper. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000494 [article] An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores [texte imprimé] / B. Krill, Auteur ; A. Ahmad, Auteur ; A. Amira, Auteur . - 2012 . - pp. 377–387. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 377–387 Mots-clés : Dynamic  partial  reconfiguration  (DPR)  Design  flow  Field  programmable  gate  array  (FPGA)  IP  cores  Image  and  signal  processing Résumé : This paper describes a dynamic partial reconfiguration (DPR) design flow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design flow, important features such as overall flexibility, application and standardised interfaces, host applications and DPR area/size placement have been taken into consideration in the proposed design flow and environment. Three intellectual property (IP) cores used in pre-processing and transform blocks of compression systems including colour space conversion (CSC), two-dimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar wavelet transform (3-D HWT) have been selected to validate the proposed DPR design flow and environment. Results obtained reveal that the proposed environment has a better solution providing: a scriptable program to establish the communication between the field programmable gate array (FPGA) with IP cores and their host application, power consumption estimation for partial reconfiguration area and automatic generation of the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of efficient IP cores with optimised area/speed ratios. Analysis of the bitstream size and dynamic power consumption for both static and reconfigurable areas is also presented in this paper. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000494

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