| Titre : | Hardware design of motion data decoding process for H.264/AVC (2010) |
| Auteurs : | Kiwon Yoo, Auteur ; Kwanghoon Sohn, Auteur |
| Type de document : | Article : texte imprimé |
| Dans : | Signal processing. Image communication (Vol. 25 N° 3 (02 ex.), Mars 2010) |
| Article en page(s) : | pp. 208–223 |
| Note générale : | Electronique |
| Langues : | Anglais |
| Index. décimale : | 621.382 (Dispositifs électroniques utilisant les effets des corps solides. Dispositifs semi-conducteurs) |
| Tags : | H.264/AVC Motion vector derivation data decoding Hardware design VLSI |
| Résumé : | In H.264/AVC, motion data can be basically derived by the following two schemes: one is a typical spatial prediction scheme based on the DPCM and the other is a sophisticated spatiotemporal prediction scheme for the skipped motion data, formally referred to as a direct mode. We verified through instruction level profiling that when these schemes are combined with various H.264/AVC coding techniques, the computational burden to derive the motion data could be considerably aggravated. Specifically, its computational complexity amounts to maximally 55% of that of the overall syntax parsing process. In this paper, we aim at an efficient hardware design of the motion data decoding process for H.264/AVC, for which all the key design considerations are addressed in detail and respective rational answers are presented. As comparing the resulting hardware design with the processor-based solution, its effectiveness was clearly demonstrated. The proposed design was implemented with 43.2 K logic gates and three on-chip memories of 3584 bits using Samsung Semiconductor’s Standard Cell Library in 65 nm L6LP process technology (SS65LP), and was capable of operating the H.264/AVC high-profile video bitstream of 1080p@60fps at 100 MHz consuming 843 μW. |
| DEWEY : | 361.382 |
| ISSN : | 0923-5965 |
| En ligne : | http://www.sciencedirect.com/science/article/pii/S0923596509001362 |
