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An efficient VLSI architecture for CBAC of AVS HDTV decoder / Junhao Zheng in Signal processing. Image communication, Vol. 24 N° 4 (Avril 2009) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 24 N° 4 (Avril 2009) . - pp. 324-332 Titre : An efficient VLSI architecture for CBAC of AVS HDTV decoder Type de document : texte imprimé Auteurs : Junhao Zheng, Auteur ; Wen Gao, Auteur ; Wu, David, Auteur Article en page(s) : pp. 324-332 Note générale : Electronique Langues : Anglais (eng) Mots-clés : CBAC  AVS  VLSI  HDTV Index. décimale : 621.382 Dispositifs électroniques utilisant les effets des corps solides. Dispositifs semi-conducteurs Résumé : Context-based Binary Arithmetic Coding (CBAC) is a normative part of the newest X Profile of Advanced Audio Video coding Standard (AVS). This paper presents an efficient VLSI architecture for CBAC decoding in AVS. Compared with CBAC in H.264/AVC, the simpler binarization methods and context selection schemes are adopted in AVS. In order to avoid the slow multiplications, the traditional arithmetic calculation is transformed to the logarithm domain. Although these features can obtain better balance between the compression gain and implementation cost, it still brings huge challenge for high-throughput implementation. The fact that current bin decoding depends on previous bin results in long latency and limits overall system performance. In this paper, we present a software–hardware co-design by using bin distribution feature. A novel pipeline-based architecture is proposed where the arithmetic decoding engine works in parallel with the context maintainer. A finite state machine (FSM) is used to control the decoding procedure flexibly and the context scheduling is organized carefully to minimize the access times of context RAMs. In addition, the critical path is optimized for the timing. The proposed implementation can work at 150 MHz and achieve the real-time AVS CBAC decoding for 1080i HDTV video. DEWEY : 361.382 ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science?_ob=PublicationURL&_tockey=%23TOC%235640%23 [...] [article] An efficient VLSI architecture for CBAC of AVS HDTV decoder [texte imprimé] / Junhao Zheng, Auteur ; Wen Gao, Auteur ; Wu, David, Auteur . - pp. 324-332. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 24 N° 4 (Avril 2009) . - pp. 324-332 Mots-clés : CBAC  AVS  VLSI  HDTV Index. décimale : 621.382 Dispositifs électroniques utilisant les effets des corps solides. Dispositifs semi-conducteurs Résumé : Context-based Binary Arithmetic Coding (CBAC) is a normative part of the newest X Profile of Advanced Audio Video coding Standard (AVS). This paper presents an efficient VLSI architecture for CBAC decoding in AVS. Compared with CBAC in H.264/AVC, the simpler binarization methods and context selection schemes are adopted in AVS. In order to avoid the slow multiplications, the traditional arithmetic calculation is transformed to the logarithm domain. Although these features can obtain better balance between the compression gain and implementation cost, it still brings huge challenge for high-throughput implementation. The fact that current bin decoding depends on previous bin results in long latency and limits overall system performance. In this paper, we present a software–hardware co-design by using bin distribution feature. A novel pipeline-based architecture is proposed where the arithmetic decoding engine works in parallel with the context maintainer. A finite state machine (FSM) is used to control the decoding procedure flexibly and the context scheduling is organized carefully to minimize the access times of context RAMs. In addition, the critical path is optimized for the timing. The proposed implementation can work at 150 MHz and achieve the real-time AVS CBAC decoding for 1080i HDTV video. DEWEY : 361.382 ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science?_ob=PublicationURL&_tockey=%23TOC%235640%23 [...]