Selecting profitable custom instructions for area–time-efficient realization on reconfigurable architectures / Lam, Siew-Kei in IEEE transactions on industrial electronics, Vol. 56 N° 10 (Octobre 2009)  

Public ISBD [article]  inIEEE transactions on industrial electronics > Vol. 56 N° 10 (Octobre 2009) . - pp. 3998 - 4005 Titre : Selecting profitable custom instructions for area–time-efficient realization on reconfigurable architectures Type de document : texte imprimé Auteurs : Lam, Siew-Kei, Auteur ; Srikanthan, Thambipillai, Auteur ; Clarke, Christopher T., Auteur Article en page(s) : pp. 3998 - 4005 Note générale : Génie électrique Langues : Anglais (eng) Mots-clés : Custom instruction selection Embedded systems High-level estimation Reconfigurable hardware Index. décimale : 621.38 Dispositifs électroniques. Tubes à électrons. Photocellules. Accélérateurs de particules. Tubes à rayons X Résumé : Profitable custom instructions provide higher performance for a given reconfigurable area. Hence, choosing profitable custom instructions that are also area-time efficient is essential if design constraints must be met by field-programmable-gate-array (FPGA)-based reconfigurable processors. In this paper, we propose a framework for FPGA-based reconfigurable processors in order to rapidly identify a reduced set of profitable custom instructions without the need for actual hardware synthesis. The proposed framework is capable of estimating the area utilization and latencies of custom instructions on lookup-table-based commercial FPGAs. Simulations based on 15 applications from benchmark suites show that the proposed method provides, on average, an area reduction of over 29% for loss of mere 1.3% in compute performance. Our evaluations also confirm that the proposed framework is superior to an existing area-optimization approach that relies on exploiting the regularity of custom instruction data paths. In particular, an average area-time product gain of over 59% was achieved by deploying a reduced set of custom instructions obtained using the proposed framework. DEWEY : 621.38 ISSN : 0278-0046 En ligne : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4801753 [article] Selecting profitable custom instructions for area–time-efficient realization on reconfigurable architectures [texte imprimé] / Lam, Siew-Kei, Auteur ; Srikanthan, Thambipillai, Auteur ; Clarke, Christopher T., Auteur . - pp. 3998 - 4005. Génie électrique Langues : Anglais (eng) in IEEE transactions on industrial electronics > Vol. 56 N° 10 (Octobre 2009) . - pp. 3998 - 4005 Mots-clés : Custom instruction selection Embedded systems High-level estimation Reconfigurable hardware Index. décimale : 621.38 Dispositifs électroniques. Tubes à électrons. Photocellules. Accélérateurs de particules. Tubes à rayons X Résumé : Profitable custom instructions provide higher performance for a given reconfigurable area. Hence, choosing profitable custom instructions that are also area-time efficient is essential if design constraints must be met by field-programmable-gate-array (FPGA)-based reconfigurable processors. In this paper, we propose a framework for FPGA-based reconfigurable processors in order to rapidly identify a reduced set of profitable custom instructions without the need for actual hardware synthesis. The proposed framework is capable of estimating the area utilization and latencies of custom instructions on lookup-table-based commercial FPGAs. Simulations based on 15 applications from benchmark suites show that the proposed method provides, on average, an area reduction of over 29% for loss of mere 1.3% in compute performance. Our evaluations also confirm that the proposed framework is superior to an existing area-optimization approach that relies on exploiting the regularity of custom instruction data paths. In particular, an average area-time product gain of over 59% was achieved by deploying a reduced set of custom instructions obtained using the proposed framework. DEWEY : 621.38 ISSN : 0278-0046 En ligne : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4801753

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