3D Integrated water cooling of a composite multilayer stack of chips / Fabio Alfieri in Journal of heat transfer, Vol. 132 N° 12 (Décembre 2010)  

Public ISBD [article]  inJournal of heat transfer > Vol. 132 N° 12 (Décembre 2010) . - pp.[121402-1/9] Titre : 3D Integrated water cooling of a composite multilayer stack of chips Type de document : texte imprimé Auteurs : Fabio Alfieri, Auteur ; Manish K. Tiwari, Auteur ; Igor Zinovik, Auteur Année de publication : 2010 Article en page(s) : pp.[121402-1/9] Note générale : Physique Langues : Anglais (eng) Mots-clés : 3D chip stack Micropin-fun Integrated water cooling Conjugate heat transfer modeling Variable properties Thin porous medium Nonthermal equilibrium Index. décimale : 536 Chaleur. Thermodynamique Résumé : New generation supercomputers with three dimensional stacked chip architectures pose a major challenge with respect to the removal of dissipated heat, which can reach currently as high as 250 W/cm2 in multilayer chip stacks of less than 0.3 cm3 volume. Interlayer integrated water cooling is a very promising approach for such high heat flux removal due to much larger thermal capacity and conductivity of water compared with air, the traditional cooling fluid. In the current work, a multiscale conjugate heat transfer model is developed for integrated water cooling of chip layers and validated with experimental measurements on an especially designed thermal test vehicle that simulates a four tier chip stack with a footprint of 1 cm2. The cooling heat transfer structure, which consists of microchannels with cylindrical pin-fins, is conceived in such a way that it can be directly integrated with the device layout in multilayer chips. Every composite layer is cooled by water flow in microchannels (height of 100 µm), which are arranged in two port water inlet-outlet configuration. The total power removed in the stack is 390 W at a temperature gradient budget of 60 K from liquid inlet to maximal junction temperature, corresponding to about 1.3 kW/cm3 volumetric heat flow. The computational cost and complexity of detailed computational fluid dynamics (CFD) modeling of heat transfer in stacked chips with integrated cooling can be prohibitive. Therefore, the heat transfer structure is modeled using a porous medium approach, where the model parameters of heat transfer and hydrodynamic resistance are derived from averaging the results of the detailed 3D-CFD simulations of a single streamwise row of fins. The modeling results indicate that an isotropic porous medium model does not accurately predict the measured temperature fields. The variation of material properties due to temperature gradients is found to be large; therefore, variable properties are used in the model. It is also shown that the modeling of the heat transfer in the cooling sublayers requires the implementation of a porous medium approach with a local thermal nonequilibrium, as well as orthotropic heat conduction and hydrodynamic resistance. The improved model reproduces the temperatures measured in the stack within 10%. The model is used to predict the behavior of multilayer stacks mimicking the change of heat fluxes resulting from variations in the computational load of the chips during their operation. DEWEY : 536 ISSN : 0022-1481 En ligne : http://asmedl.aip.org/vsearch/servlet/VerityServlet?KEY=JHTRAO&ONLINE=YES&smode= [...] [article] 3D Integrated water cooling of a composite multilayer stack of chips [texte imprimé] / Fabio Alfieri, Auteur ; Manish K. Tiwari, Auteur ; Igor Zinovik, Auteur . - 2010 . - pp.[121402-1/9]. Physique Langues : Anglais (eng) in Journal of heat transfer > Vol. 132 N° 12 (Décembre 2010) . - pp.[121402-1/9] Mots-clés : 3D chip stack Micropin-fun Integrated water cooling Conjugate heat transfer modeling Variable properties Thin porous medium Nonthermal equilibrium Index. décimale : 536 Chaleur. Thermodynamique Résumé : New generation supercomputers with three dimensional stacked chip architectures pose a major challenge with respect to the removal of dissipated heat, which can reach currently as high as 250 W/cm2 in multilayer chip stacks of less than 0.3 cm3 volume. Interlayer integrated water cooling is a very promising approach for such high heat flux removal due to much larger thermal capacity and conductivity of water compared with air, the traditional cooling fluid. In the current work, a multiscale conjugate heat transfer model is developed for integrated water cooling of chip layers and validated with experimental measurements on an especially designed thermal test vehicle that simulates a four tier chip stack with a footprint of 1 cm2. The cooling heat transfer structure, which consists of microchannels with cylindrical pin-fins, is conceived in such a way that it can be directly integrated with the device layout in multilayer chips. Every composite layer is cooled by water flow in microchannels (height of 100 µm), which are arranged in two port water inlet-outlet configuration. The total power removed in the stack is 390 W at a temperature gradient budget of 60 K from liquid inlet to maximal junction temperature, corresponding to about 1.3 kW/cm3 volumetric heat flow. The computational cost and complexity of detailed computational fluid dynamics (CFD) modeling of heat transfer in stacked chips with integrated cooling can be prohibitive. Therefore, the heat transfer structure is modeled using a porous medium approach, where the model parameters of heat transfer and hydrodynamic resistance are derived from averaging the results of the detailed 3D-CFD simulations of a single streamwise row of fins. The modeling results indicate that an isotropic porous medium model does not accurately predict the measured temperature fields. The variation of material properties due to temperature gradients is found to be large; therefore, variable properties are used in the model. It is also shown that the modeling of the heat transfer in the cooling sublayers requires the implementation of a porous medium approach with a local thermal nonequilibrium, as well as orthotropic heat conduction and hydrodynamic resistance. The improved model reproduces the temperatures measured in the stack within 10%. The model is used to predict the behavior of multilayer stacks mimicking the change of heat fluxes resulting from variations in the computational load of the chips during their operation. DEWEY : 536 ISSN : 0022-1481 En ligne : http://asmedl.aip.org/vsearch/servlet/VerityServlet?KEY=JHTRAO&ONLINE=YES&smode= [...]

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