Multilayered image processing for multiscale harris corner detection in digital realization / Hsiao, Pei-Yung in IEEE transactions on industrial electronics, Vol. 57 N° 5 (Mai 2010)  

Public ISBD [article]  inIEEE transactions on industrial electronics > Vol. 57 N° 5 (Mai 2010) . - pp. 1799 - 1805 Titre : Multilayered image processing for multiscale harris corner detection in digital realization Type de document : texte imprimé Auteurs : Hsiao, Pei-Yung, Auteur ; Lu, Chieh-Lun, Auteur ; Fu, Li-Chen, Auteur Année de publication : 2011 Article en page(s) : pp. 1799 - 1805 Note générale : Génie électrique Langues : Anglais (eng) Mots-clés : Field-programmable gate array (FPGA) Multilayered image processing Multiscale Harris corner detection Pattern recognition Index. décimale : 621.38 Dispositifs électroniques. Tubes à électrons. Photocellules. Accélérateurs de particules. Tubes à rayons X Résumé : The PC-based software programming used in complex or luxuriant image processing algorithms is time consuming and resource wasting. As appropriate processing for the image data indeed speedups complicated algorithms, we focus on a crucial case - multilayered processes. In this paper, we gauge deeply into the data flow of multilayered image processing to avoid waiting for the result from every previous steps to access the memory which occurs in many applicable algorithms. Based on combining the parallel and pipelined properties to eliminate unnecessary delays, we propose new visual pipeline architecture and use field programmable gate array to implement our hardware scheme. For verification, the multiscale Harris corner detector in cooperating with shape context and thin-plate splines were combined to complete our real-time experiment of the integrated hardware and software (H/S) system for pattern recognition. DEWEY : 621.38 ISSN : 0278-0046 En ligne : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5409580 [article] Multilayered image processing for multiscale harris corner detection in digital realization [texte imprimé] / Hsiao, Pei-Yung, Auteur ; Lu, Chieh-Lun, Auteur ; Fu, Li-Chen, Auteur . - 2011 . - pp. 1799 - 1805. Génie électrique Langues : Anglais (eng) in IEEE transactions on industrial electronics > Vol. 57 N° 5 (Mai 2010) . - pp. 1799 - 1805 Mots-clés : Field-programmable gate array (FPGA) Multilayered image processing Multiscale Harris corner detection Pattern recognition Index. décimale : 621.38 Dispositifs électroniques. Tubes à électrons. Photocellules. Accélérateurs de particules. Tubes à rayons X Résumé : The PC-based software programming used in complex or luxuriant image processing algorithms is time consuming and resource wasting. As appropriate processing for the image data indeed speedups complicated algorithms, we focus on a crucial case - multilayered processes. In this paper, we gauge deeply into the data flow of multilayered image processing to avoid waiting for the result from every previous steps to access the memory which occurs in many applicable algorithms. Based on combining the parallel and pipelined properties to eliminate unnecessary delays, we propose new visual pipeline architecture and use field programmable gate array to implement our hardware scheme. For verification, the multiscale Harris corner detector in cooperating with shape context and thin-plate splines were combined to complete our real-time experiment of the integrated hardware and software (H/S) system for pattern recognition. DEWEY : 621.38 ISSN : 0278-0046 En ligne : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5409580

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