Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators / Yiran Li in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010)  

Public ISBD [article]  inSignal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 335–344 Titre : Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators Type de document : texte imprimé Auteurs : Yiran Li, Auteur ; Yang Liu, Auteur ; Tong Zhang, Auteur Année de publication : 2012 Article en page(s) : pp. 335–344 Note générale : Electronique Langues : Anglais (eng) Mots-clés : Motion estimation (ME) 3D memory stacking Résumé : Enabled by the emerging three-dimensional (3D) integration technologies, 3D integrated computing platforms that stack high-density DRAM die(s) with a logic circuit die appear to be attractive for memory-hungry applications such as multimedia signal processing. This paper considers the design of motion estimation accelerator under a 3D logic-DRAM integrated heterogeneous multi-core system framework. In this work, we develop one specific DRAM organization and image frame storage strategy geared to motion estimation. This design strategy can seamlessly support various motion estimation algorithms and variable block size with high energy efficiency. With a DRAM performance modeling/estimation tool and ASIC design at 65 nm, we demonstrate the energy efficiency of such 3D integrated motion estimation accelerators with a case study on HDTV multi-frame motion estimation. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000469 [article] Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators [texte imprimé] / Yiran Li, Auteur ; Yang Liu, Auteur ; Tong Zhang, Auteur . - 2012 . - pp. 335–344. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 335–344 Mots-clés : Motion estimation (ME) 3D memory stacking Résumé : Enabled by the emerging three-dimensional (3D) integration technologies, 3D integrated computing platforms that stack high-density DRAM die(s) with a logic circuit die appear to be attractive for memory-hungry applications such as multimedia signal processing. This paper considers the design of motion estimation accelerator under a 3D logic-DRAM integrated heterogeneous multi-core system framework. In this work, we develop one specific DRAM organization and image frame storage strategy geared to motion estimation. This design strategy can seamlessly support various motion estimation algorithms and variable block size with high energy efficiency. With a DRAM performance modeling/estimation tool and ASIC design at 65 nm, we demonstrate the energy efficiency of such 3D integrated motion estimation accelerators with a case study on HDTV multi-frame motion estimation. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000469

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