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An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores / B. Krill in Signal processing. Image communication, Vol. 25 N° 5 (Juin 2010) 

Public ISBD [article]  in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 377–387 Titre : An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores Type de document : texte imprimé Auteurs : B. Krill, Auteur ; A. Ahmad, Auteur ; A. Amira, Auteur Année de publication : 2012 Article en page(s) : pp. 377–387 Note générale : Electronique Langues : Anglais (eng) Mots-clés : Dynamic  partial  reconfiguration  (DPR)  Design  flow  Field  programmable  gate  array  (FPGA)  IP  cores  Image  and  signal  processing Résumé : This paper describes a dynamic partial reconfiguration (DPR) design flow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design flow, important features such as overall flexibility, application and standardised interfaces, host applications and DPR area/size placement have been taken into consideration in the proposed design flow and environment. Three intellectual property (IP) cores used in pre-processing and transform blocks of compression systems including colour space conversion (CSC), two-dimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar wavelet transform (3-D HWT) have been selected to validate the proposed DPR design flow and environment. Results obtained reveal that the proposed environment has a better solution providing: a scriptable program to establish the communication between the field programmable gate array (FPGA) with IP cores and their host application, power consumption estimation for partial reconfiguration area and automatic generation of the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of efficient IP cores with optimised area/speed ratios. Analysis of the bitstream size and dynamic power consumption for both static and reconfigurable areas is also presented in this paper. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000494 [article] An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores [texte imprimé] / B. Krill, Auteur ; A. Ahmad, Auteur ; A. Amira, Auteur . - 2012 . - pp. 377–387. Electronique Langues : Anglais (eng) in Signal processing. Image communication > Vol. 25 N° 5 (Juin 2010) . - pp. 377–387 Mots-clés : Dynamic  partial  reconfiguration  (DPR)  Design  flow  Field  programmable  gate  array  (FPGA)  IP  cores  Image  and  signal  processing Résumé : This paper describes a dynamic partial reconfiguration (DPR) design flow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design flow, important features such as overall flexibility, application and standardised interfaces, host applications and DPR area/size placement have been taken into consideration in the proposed design flow and environment. Three intellectual property (IP) cores used in pre-processing and transform blocks of compression systems including colour space conversion (CSC), two-dimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar wavelet transform (3-D HWT) have been selected to validate the proposed DPR design flow and environment. Results obtained reveal that the proposed environment has a better solution providing: a scriptable program to establish the communication between the field programmable gate array (FPGA) with IP cores and their host application, power consumption estimation for partial reconfiguration area and automatic generation of the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of efficient IP cores with optimised area/speed ratios. Analysis of the bitstream size and dynamic power consumption for both static and reconfigurable areas is also presented in this paper. ISSN : 0923-5965 En ligne : http://www.sciencedirect.com/science/article/pii/S0923596510000494