Design of Low Complex Non Binary LDPC Decoder using Min - Max algorithm / Kamel-eddine Harabi (2017) 

Public ISBD Titre : Design of Low Complex Non Binary LDPC Decoder using Min - Max algorithm Type de document : texte imprimé Auteurs : Kamel-eddine Harabi, Auteur ; M. Taghi, Directeur de thèse Editeur : [S.l.] : [s.n.] Année de publication : 2017 Importance : 29 f. Présentation : ill. Format : 30 cm. Accompagnement : 1 CD-ROM. Note générale : Mémoire de Master : Electronique : Alger, Ecole Nationale Polytechnique : 2017 Bibliogr. f. 28 - 29 Langues : Anglais (eng) Mots-clés : LDPC Galois Field NB-LDPC Min-Max Decoder Architecture Design Implementation Index. décimale : Ms14417 Résumé : Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called Non-Binary LDPC (NB-LDPC) codes, are an extension of binary LDPC codes with significantly better performance. The design and implementation of NB-LDPC decoders has rarely been discussed due to their hardware implementation complexity. In this project, we focused on the design of low complex architecture for a NB-LDPC decoder using the Min-Max decoding algorithm.. The main contributions of this work correspond to the design of the decoder basic bloc ks, as the check node (CN) block, the variable node (VN) block and the codeword decision block with efficiency techniques. The design of the decoder and its components are detailed, Various details like block schematics and the components functionality and explanation examples have been presented and documented. Design of Low Complex Non Binary LDPC Decoder using Min - Max algorithm [texte imprimé] / Kamel-eddine Harabi, Auteur ; M. Taghi, Directeur de thèse . - [S.l.] : [s.n.], 2017 . - 29 f. : ill. ; 30 cm. + 1 CD-ROM. Mémoire de Master : Electronique : Alger, Ecole Nationale Polytechnique : 2017 Bibliogr. f. 28 - 29 Langues : Anglais (eng) Mots-clés : LDPC Galois Field NB-LDPC Min-Max Decoder Architecture Design Implementation Index. décimale : Ms14417 Résumé : Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called Non-Binary LDPC (NB-LDPC) codes, are an extension of binary LDPC codes with significantly better performance. The design and implementation of NB-LDPC decoders has rarely been discussed due to their hardware implementation complexity. In this project, we focused on the design of low complex architecture for a NB-LDPC decoder using the Min-Max decoding algorithm.. The main contributions of this work correspond to the design of the decoder basic bloc ks, as the check node (CN) block, the variable node (VN) block and the codeword decision block with efficiency techniques. The design of the decoder and its components are detailed, Various details like block schematics and the components functionality and explanation examples have been presented and documented.

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Code-barres	Cote	Support	Localisation	Section	Disponibilité	Spécialité	Etat_Exemplaire
S000123	Ms14417	Papier + ressource électronique	Bibliothèque Annexe	Mémoire de Master	Disponible	Electronique	Consultation sur place/Téléchargeable

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HARABI.Kamel-Eddine.pdf URL

Implementation of non binary LDPC decoder on FPGA for wireless communication systems / Cherif Bali (2017) 

Public ISBD Titre : Implementation of non binary LDPC decoder on FPGA for wireless communication systems Type de document : texte imprimé Auteurs : Cherif Bali, Auteur ; Kamel-eddine Harabi, Auteur ; M. Taghi, Directeur de thèse Editeur : [S.l.] : [s.n.] Année de publication : 2017 Importance : 75 f. Présentation : ill. Format : 30 cm. Accompagnement : 1 CD-ROM Note générale : Mémoire de Projet de Fin d'Etudes : Electronique : Alger, Ecole Nationale Polytechnique : 2017 Bibliogr. f. 74 - 75 Langues : Anglais (eng) Mots-clés : LDPC NB-LDPC Shannon limit Error correction Min-Max Decoder Archi-tecture Design Implementation Index. décimale : PN00217 Résumé : Low Density Parity-Check (LDPC) codes have been successfully included in numerous wireless communication standards, since they achieve error correction performance very close to the Shannon limit. Non-Binary LDPC codes has better performance than the binary LDPC codes, In this thesis, we focused on the design and implementation of efficient ar-chitecture of the NB-LDPC decoder basic blocks using the Min-Max algorithm. In order to provide flexible decoder. The design and implementation of the decoder components are detailed. Various details like block schematics and simulation have been documented. Implementation of non binary LDPC decoder on FPGA for wireless communication systems [texte imprimé] / Cherif Bali, Auteur ; Kamel-eddine Harabi, Auteur ; M. Taghi, Directeur de thèse . - [S.l.] : [s.n.], 2017 . - 75 f. : ill. ; 30 cm. + 1 CD-ROM. Mémoire de Projet de Fin d'Etudes : Electronique : Alger, Ecole Nationale Polytechnique : 2017 Bibliogr. f. 74 - 75 Langues : Anglais (eng) Mots-clés : LDPC NB-LDPC Shannon limit Error correction Min-Max Decoder Archi-tecture Design Implementation Index. décimale : PN00217 Résumé : Low Density Parity-Check (LDPC) codes have been successfully included in numerous wireless communication standards, since they achieve error correction performance very close to the Shannon limit. Non-Binary LDPC codes has better performance than the binary LDPC codes, In this thesis, we focused on the design and implementation of efficient ar-chitecture of the NB-LDPC decoder basic blocks using the Min-Max algorithm. In order to provide flexible decoder. The design and implementation of the decoder components are detailed. Various details like block schematics and simulation have been documented.

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Code-barres	Cote	Support	Localisation	Section	Disponibilité	Spécialité	Etat_Exemplaire
P000024	PN00217	Papier + ressource électronique	Bibliothèque centrale	Projet Fin d'Etudes	Disponible	Electronique	Consultation sur place/Téléchargeable

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BALI.Cherif_HARABI.Kamel-eddine.pdf URL