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Implementation of non binary LDPC decoder on FPGA for wireless communication systems / Cherif Bali

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Titre : Implementation of non binary LDPC decoder on FPGA for wireless communication systems
Type de document : texte imprimé
Auteurs : Cherif Bali, Auteur ; Kamel-eddine Harabi, Auteur ; M. Taghi, Directeur de thèse
Editeur : [S.l.] : [s.n.]
Année de publication : 2017
Importance : 75 f.
Présentation : ill.
Format : 30 cm.
Accompagnement : 1 CD-ROM
Note générale : Mémoire de Projet de Fin d'Etudes : Electronique : Alger, Ecole Nationale Polytechnique : 2017
Bibliogr. f. 74 - 75
Langues : Anglais (eng)
Mots-clés : LDPC
NB-LDPC
Shannon limit
Error correction
Min-Max
Decoder
Archi-tecture
Design
Implementation
Index. décimale : PN00217
Résumé : Low Density Parity-Check (LDPC) codes have been successfully included in numerous wireless communication standards, since they achieve error correction performance very close to the Shannon limit.
Non-Binary LDPC codes has better performance than the binary LDPC codes, In this thesis, we focused on the design and implementation of efficient ar-chitecture of the NB-LDPC decoder basic blocks using the Min-Max algorithm.
In order to provide flexible decoder.
The design and implementation of the decoder components are detailed.
Various details like block schematics and simulation have been documented.

Implementation of non binary LDPC decoder on FPGA for wireless communication systems [texte imprimé] / Cherif Bali, Auteur ; Kamel-eddine Harabi, Auteur ; M. Taghi, Directeur de thèse . - [S.l.] : [s.n.], 2017 . - 75 f. : ill. ; 30 cm. + 1 CD-ROM.
Mémoire de Projet de Fin d'Etudes : Electronique : Alger, Ecole Nationale Polytechnique : 2017
Bibliogr. f. 74 - 75
Langues : Anglais (eng)
Mots-clés : LDPC
NB-LDPC
Shannon limit
Error correction
Min-Max
Decoder
Archi-tecture
Design
Implementation
Index. décimale : PN00217
Résumé : Low Density Parity-Check (LDPC) codes have been successfully included in numerous wireless communication standards, since they achieve error correction performance very close to the Shannon limit.
Non-Binary LDPC codes has better performance than the binary LDPC codes, In this thesis, we focused on the design and implementation of efficient ar-chitecture of the NB-LDPC decoder basic blocks using the Min-Max algorithm.
In order to provide flexible decoder.
The design and implementation of the decoder components are detailed.
Various details like block schematics and simulation have been documented.

Exemplaires

Code-barres Cote Support Localisation Section Disponibilité Spécialité Etat_Exemplaire
P000024 PN00217 Papier + ressource électronique Bibliothèque centrale Projet Fin d'Etudes Disponible Electronique Consultation sur place/Téléchargeable

Documents numériques

BALI.Cherif_HARABI.Kamel-eddine.pdf
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